Comments for mikestirling.co.uk http://mikestirling.co.uk Tue, 07 Feb 2012 12:41:21 +0000 hourly 1 http://wordpress.org/?v=3.3.1 Comment on BBC Micro on an FPGA by Stephen http://mikestirling.co.uk/bbc-micro-on-an-fpga/comment-page-1/#comment-12846 Stephen Tue, 07 Feb 2012 12:41:21 +0000 http://mikestirling.co.uk/?page_id=93#comment-12846 Minor modification to the CRTC.. I needed to stop the half line phase shift on alternate frames. I basically write a byte to a fifo on every vid_clken, when the fifo has 4 bytes i write that to DDR ram (via Xilinx MIG). The reading bit is trickier but it does scandouble although i havent done the deinterlace properly yet. Thats only *really* important in mode 7. Its outputing via HDMI on the Atlys but it could easily be modified to output to VGA on something else. I'm now working on getting a Tube interface working. I'll keep you updated. Minor modification to the CRTC.. I needed to stop the half line phase shift on alternate frames.

I basically write a byte to a fifo on every vid_clken, when the fifo has 4 bytes i write that to DDR ram (via Xilinx MIG). The reading bit is trickier but it does scandouble although i havent done the deinterlace properly yet. Thats only *really* important in mode 7.

Its outputing via HDMI on the Atlys but it could easily be modified to output to VGA on something else.

I’m now working on getting a Tube interface working. I’ll keep you updated.

]]> Comment on BBC Micro on an FPGA by Mike http://mikestirling.co.uk/bbc-micro-on-an-fpga/comment-page-1/#comment-12807 Mike Mon, 06 Feb 2012 21:35:14 +0000 http://mikestirling.co.uk/?page_id=93#comment-12807 Excellent! Is that running on a PC monitor, and if so did you implement a scan doubler, or modify the CRTC? Excellent! Is that running on a PC monitor, and if so did you implement a scan doubler, or modify the CRTC?

]]> Comment on BBC Micro on an FPGA by Stephen http://mikestirling.co.uk/bbc-micro-on-an-fpga/comment-page-1/#comment-12784 Stephen Mon, 06 Feb 2012 12:38:24 +0000 http://mikestirling.co.uk/?page_id=93#comment-12784 Mike, i've managed to get this working lovely on the Digilent Atlys. Here are a couple of videos of it working. http://www.youtube.com/watch?v=wFtVTaFZ5Lo http://www.youtube.com/watch?v=1cYkE3jPCRg Mike, i’ve managed to get this working lovely on the Digilent Atlys. Here are a couple of videos of it working.

http://www.youtube.com/watch?v=wFtVTaFZ5Lo

http://www.youtube.com/watch?v=1cYkE3jPCRg

]]> Comment on ZX Spectrum on an FPGA by Mike http://mikestirling.co.uk/zx-spectrum-on-an-fpga/comment-page-1/#comment-12524 Mike Wed, 01 Feb 2012 21:11:41 +0000 http://mikestirling.co.uk/?page_id=173#comment-12524 Hi Lez, This sounds interesting like an interesting project. You are correct about the T80 not being cycle accurate, although it is not something I have had time to look into yet. I think a major problem with achieving perfect timing when modelling these old devices is that many of them are wholly or partly asynchronous in their design. With the speeds at which modern FPGAs operate it is an absolute necessity to keep the design completely synchronous, and this necessarily introduces extra clock cycles that can affect the relative timing of different operations. You should also take a look at the <a href="http://zxprism.blogspot.com/" title="ZX Prism" target="_blank" rel="nofollow">ZX Prism</a>, as I know that Jeff has spent some time investigating timing accuracy. Mike Hi Lez,

This sounds interesting like an interesting project. You are correct about the T80 not being cycle accurate, although it is not something I have had time to look into yet. I think a major problem with achieving perfect timing when modelling these old devices is that many of them are wholly or partly asynchronous in their design. With the speeds at which modern FPGAs operate it is an absolute necessity to keep the design completely synchronous, and this necessarily introduces extra clock cycles that can affect the relative timing of different operations.

You should also take a look at the ZX Prism, as I know that Jeff has spent some time investigating timing accuracy.

Mike

]]> Comment on ZX Spectrum on an FPGA by Lez Anderson http://mikestirling.co.uk/zx-spectrum-on-an-fpga/comment-page-1/#comment-12514 Lez Anderson Wed, 01 Feb 2012 16:04:42 +0000 http://mikestirling.co.uk/?page_id=173#comment-12514 Hi. Myself and another chap are currently in the feasibility/Early stages of putting a Memotexh MTX512 onto a FPGA board. Having looked at your website I was VERY impressed at what you'd done for the ZX Spectrum! However we are having some timing issues and incompatibility problems with the T80. As it seems not to work like a true Z80A! I wondered if it was possible to 'pick' your large Brain and get some hints on what may be the problem ?? Any guidance and help would be much appreciated. Kind Regards Lez Hi.

Myself and another chap are currently in the feasibility/Early stages of putting a Memotexh MTX512 onto a FPGA board.

Having looked at your website I was VERY impressed at what you’d done for the ZX Spectrum!

However we are having some timing issues and incompatibility problems with the T80. As it seems not to work like a true Z80A!

I wondered if it was possible to ‘pick’ your large Brain and get some hints on what may be the problem ??

Any guidance and help would be much appreciated.

Kind Regards

Lez

]]> Comment on Design Detail by Simon Ellwood http://mikestirling.co.uk/bbc-micro-on-an-fpga/bbc-micro-on-an-fpga-design-detail/comment-page-1/#comment-12509 Simon Ellwood Wed, 01 Feb 2012 14:21:03 +0000 http://mikestirling.co.uk/?page_id=111#comment-12509 For the floppy interface consider using a 1770 disk controller instead. This will then be ADFS compatible. There is a HDL model of the similar 1772 disk controller in the Suska open source Atari ST project! Great work by the way I will try it on my DE1 when I get time. Cheers. For the floppy interface consider using a 1770 disk controller instead. This will then be ADFS compatible. There is a HDL model of the similar 1772 disk controller in the Suska open source Atari ST project!

Great work by the way I will try it on my DE1 when I get time.

Cheers.

]]> Comment on ZX Spectrum on an FPGA by Silvestar http://mikestirling.co.uk/zx-spectrum-on-an-fpga/comment-page-1/#comment-12493 Silvestar Wed, 01 Feb 2012 08:47:14 +0000 http://mikestirling.co.uk/?page_id=173#comment-12493 Hi! ZX Spectrum 48K (rubber key version) was also my first home computer, back in 1985. Besides playing games I started learninig BASIC since i had it as facultative class in primary school (although experimental at that time)...Those were the days! 2 years later I replaced it with 128K version Hi!
ZX Spectrum 48K (rubber key version) was also my first home computer, back in 1985. Besides playing games I started learninig BASIC since i had it as facultative class in primary school (although experimental at that time)…Those were the days!
2 years later I replaced it with 128K version

]]> Comment on ZX Spectrum on an FPGA by ilectrologos http://mikestirling.co.uk/zx-spectrum-on-an-fpga/comment-page-1/#comment-12341 ilectrologos Sat, 28 Jan 2012 09:24:40 +0000 http://mikestirling.co.uk/?page_id=173#comment-12341 nice !!! nice !!!

]]> Comment on BBC Micro on an FPGA by Mark http://mikestirling.co.uk/bbc-micro-on-an-fpga/comment-page-1/#comment-12222 Mark Tue, 24 Jan 2012 21:14:21 +0000 http://mikestirling.co.uk/?page_id=93#comment-12222 Wow - just discovered this and your speccy project! Looks like you've done some impressive work - more than my half-completed efforts! Nice! Also had no idea there was a PAL/NTSC core... my colleague has been working on one and is almost there... he'll be interested in that no doubt! Wow – just discovered this and your speccy project! Looks like you’ve done some impressive work – more than my half-completed efforts! Nice!

Also had no idea there was a PAL/NTSC core… my colleague has been working on one and is almost there… he’ll be interested in that no doubt!

]]> Comment on BBC Micro on an FPGA by Stephen http://mikestirling.co.uk/bbc-micro-on-an-fpga/comment-page-1/#comment-11410 Stephen Thu, 05 Jan 2012 09:03:18 +0000 http://mikestirling.co.uk/?page_id=93#comment-11410 Mike, quick update. I've investigated and found that in modes 3,6 and 7 the 6845 model is not inserting the blank scanlines. This means that the VSYNC pulse is getting sent around PAL scanline 599 on those modes instead of scanline 623 on the other modes. I've not seen anything in the code yet that explains it but that would be why many people are reporting problems with syncing. Also it means that the machine doesnt get enough CPU time per frame for some of the more exotic games. I spotted this because i'm having to convolve my signal onto a DVI carrier as the Atlys doesnt have VGA. Just HDMI. Mike, quick update. I’ve investigated and found that in modes 3,6 and 7 the 6845 model is not inserting the blank scanlines. This means that the VSYNC pulse is getting sent around PAL scanline 599 on those modes instead of scanline 623 on the other modes. I’ve not seen anything in the code yet that explains it but that would be why many people are reporting problems with syncing. Also it means that the machine doesnt get enough CPU time per frame for some of the more exotic games.

I spotted this because i’m having to convolve my signal onto a DVI carrier as the Atlys doesnt have VGA. Just HDMI.

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